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Mathan, N.
- A Survey on Carbon Nanotube Field Effect Transistors
Authors
1 Department of ECE, Sathyabama University, Chennai, Tamilnadu, IN
2 Department of ECE, Sathyabama University, Chennai, Tamilnadu, IN
Source
Programmable Device Circuits and Systems, Vol 5, No 7 (2013), Pagination: 294-297Abstract
The system on chip design will integrate millions of transistors on one chip, whereas packaging and cooling only have a limited ability to remove the excess heat. CMOS devices are scaling down to nano ranges resulting in increased process variations and short channel effects which not only affect the reliability of the device but also performance expectations. With the advent of portable and high efficient microelectronic devices, the power dissipation of VLSI circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. Carbon nanotube field effect transistor (CNTFET) is a very promising and superior technology for its applications to circuit design. In this paper, an extensive survey on CNTFET are depicted which will make the future, a valuable successor in the field of electronics.Keywords
CNTFET, Ballistic CNTFET, Schottky Barrier, Top Gated CNTFET.
- A Comparative Analysis of Low Power D Flip Flop Using Leakage Power Reduction Techniques
Authors
1 Sathyabama University, Chennai, Tamilnadu, IN
Source
Automation and Autonomous Systems, Vol 4, No 6 (2012), Pagination: 237-242Abstract
This paper proposes a new topology to low power approaches for very large scale integration (VLSI) design. Power dissipation is one of the major concerns when designing a VLSI system. Until recently, dynamic power was the only concern. However, as the technology feature size shrinks, static power, which was negligible before, becomes an issue as important as dynamic power. Since static power increases dramatically in nanoscale silicon VLSI technology, the importance of reducing leakage. This paper describes a low-leakage technique. We are doing comparable analysis of different low power, leakage current reduction techniques like SLEEP approach, STACK, SLEEPY–STACK, SLEEPY KEEPER, SLEEPY–STACK with KEEPER, LEAKAGE FEEDBACK and LEAKAGE FEEDBACK with STACK techniques. Which reduces leakage power while saving exact logic state. Based on simulation results a conventional D Flip flop with the Full sleep approach achieves up to 95 % less power consumption.